In the routing and switching device, a data packet is usually divided into a plurality of data slices according to a certain rule, and when outputting the data packet, the plurality of divided data slices are combined to recover to the original data packet. The length of the data slice divided from the data packet should be relevant to factors such as the minimum length of the data packet, the processing speed of the interior packet, the data bit width of the memory, etc. Queue storage usually uses the manner of dynamically storing different queue storage areas, and under the condition that the bandwidth utilization rate of the memory is taken into consideration, queue data which needs to be cached may be put into any idle areas.
With the development of network technology, the bandwidth of dynamic data caching in the routing and switching device becomes larger and larger; due to the existence of timing requirements such as pre-charge, column activation and automatic refresh of the dynamic memory, the bandwidth utilization rate of the memory becomes the first problem which should be taken into consideration in data caching. However, the increase of port speed and the change of the data packet length cause the timing control of data caching to become complicated. Accordingly, the actual data bandwidth of the memory becomes an important reference for selecting the data caching memory devices in the routing and switching device.